The present invention relates to a semiconductor memory device, and particularly to a technique used and effective for a device using ferroelectric capacitors.
There has been known a semiconductor device provided with a plurality of ferroelectric capacitors with respect to a single switching element as shown in FIG. 32 to bring it into high integration or the like. This type of semiconductor device has been disclosed in Japanese Patent Laid-Open No. 4-90189.
The inventors of the present application have found various problems that must solve stresses placed on non-selected ferroelectric capacitors, which are inevitably produced when the plurality of ferroelectric capacitors are provided with respect to the single switching element as described above.